A Universal Processor for RAMP

The objective of the RAMP project is to accelerate multiprocessor systems research through the emulation of usable parallel processor prototypes. Criteria such as low cost, flexibility, observability, credible and repeatable results, and reasonable performance led to the choice of the FPGA platform, BEE2 (Berkeley Emulation Engine) as the primary host environment. A key goal of RAMP is the extraction of credible performance results, even from tests which are not run in real time. The need for a timing model was the original reason for RDL [12]. Credible results, however, also require the use of known tests, or applications, many of which are tied to existing instruction set architectures (ISAs). To run such tests, and finish the infrastructure phases of RAMP quickly, it is highly desireable to be able to run pre-compiled code for existing architectures. This has led to a major push among the RAMP participants to find, adapt or develop HDL descriptions of existing ISAs and, with the addition of RDL wrappers, turn them into RAMP-compatible processors. While this approach will lend signficant credibility to any results, it presents critical challenges, and will delay the project from the longerterm goal of parallel system research. In this paper we outline our proposal to drastically reduce the one-time work required to achieve ISA level compatiblility for a variety of architectures, while addressing essential research and efficiency goals. Rather than trying to acquire and adapt for FPGAs, HDL code for each processor family and model, we propose to build a single unified processor, along with tools to customize and program it. When compatibility is required, exiting code can be made to run on this processor by using binary translation. Because we would no longer attempt to synthesize gateware from an existing processor simulation model, e.g.from OpenSPARC, our unified processor can be dramatically more area-efficient, as it can have an ISA and micro-architecture tailored to FPGAs. Furthermore, by generating (possibly widely varied) processors in a uniform way, we can significantly simplify research into architectural features. The next few sections cover the problems, goals and research questions this project will address. As this is a preliminary whitepaper, we do not offer complete solutions but we do attempt to suggest them for most of the open research questions. We are also openly soliciting related ideas as well as informed suggestions and commentary.